5/26/2026
Researchers led by Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performance silicon circuits. This advance marks a critical step toward realizing the full potential of three-dimensional chips that could carry computing beyond the limits of traditional scaling.
Researchers led by Illinois Grainger Engineering professor Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performance silicon circuits. This advance marks a critical step toward realizing the full potential of three-dimensional chips that could carry computing beyond the limits of traditional scaling.
For more than half a century, the power of computers has grown by shrinking transistors and packing them more tightly onto flat chips. It worked too well. Devices are now becoming so small that they start to be fundamentally limited by atomic dimensions and quantum effects.
The next leap can come from adding a new dimension: building upward. By vertically stacking layers of silicon circuits, chipmakers can dramatically increase computing density and speed while reducing energy use, offering a promising route to extend Moore’s law without shrinking transistors any further.
“Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. ”
Associate Professor Qing Cao, Department of Materials Science and Enginering
Illinois Grainger Engineering materials science and engineering professor Qing Cao explains, “Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”
The most efficient approach, known as monolithic three-dimensional integration, builds each layer directly on top of the previous one to maximize interlayer connectivity. However, achieving this has been a longstanding technical challenge. Preparing high-quality silicon and fabricating high-performance devices normally require processes operating at 1,000 degrees Celsius, hot enough to destroy the metal wiring. For upper layers beyond the first, the temperature constraint, or “thermal budget,” is strictly set to 400 degrees.
A team of Illinois Grainger Engineering researchers led by Cao has now shown that it is possible to stay within that limit while still achieving high device performance across multiple tiers. Their newly invented process uses single-crystalline silicon — the main semiconductor used in industry — and has demonstrated device yields of 98‒100%, even in an academic laboratory cleanroom setting, indicating strong potential for industrial adoption.
“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips,” Cao said. “For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance.”
This study appears in Nature as one of the journal’s rare research articles focused on silicon microelectronics.
The work was conducted within Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, which counts IBM, Intel, and the Taiwan Semiconductor Manufacturing Company, among its industry partners. The team is now preparing to translate their process to an industrial semiconductor foundry.
Microelectronics manufacturing has been driven for the past 60 years by Moore’s law, which states that the density of transistors on a chip should double every two years. The electronics industry has adopted this principle as a production goal to increase the power and efficiency of computer processors. It has proven successful and steady for decades, but there are signs that the trend is starting to stall.
“In a sense, we’re hitting a limit imposed by physics,” Cao said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of their contacted gate pitch. This is because we’re becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we’re going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface.”
Many experts believe that the way forward will be building upward to vertically integrate devices. It gives room for expansion without further shrinking individual devices. It also shortens the needed length of wiring, reducing parasitic capacitance while dramatically increasing the communication bandwidth between devices and circuit blocks. These features offer a crucial advantage for artificial intelligence and other forms of data-intensive computing.
“If we're going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface.”
Associate Professor Qing Cao, Department of Materials Science and Engineering
Current commercial three-dimensional chips are made by fabricating semiconductor devices on separate wafer substrates first and then bonding those wafers or dies together. While this approach has enabled successful products such as high-bandwidth memory and 3D V-Cache chips, it comes with substantial limitations. The alignment between layers is necessarily coarse, and the micron-scale vertical connections between layers called through-silicon via or TSV are relatively large and sparse.
In contrast, monolithic three-dimensional integration takes a fundamentally different approach. Instead of stacking complete wafers, each device layer is sequentially built directly on top of the previous one during fabrication. This procedure allows for much (10-100 times) denser interlayer vertical connections, smaller separations between layers, and precise interlayer alignment with nanometer-scale accuracy.
The main barrier to a practical realization of this process is temperature. Forming high-quality crystalline silicon and then fabricating high-performance semiconductor devices both require temperatures close to 1,000 degrees Celsius, while the metal interconnects used to communicate between devices melt far below that point.
“Generally, the industry accepts that once the first layer of circuits is complete, the thermal budget limit for any additional layers is 400 degrees Celsius,” Cao said. “Researchers in both academia and industry have tried to get around this by working with semiconductor materials other than single-crystalline silicon for the upper layers. But the resulting devices all inevitably suffer from issues with performance and reliability.”
The alternatives that have been explored include polycrystalline silicon, amorphous or nanocrystalline metal oxides, and nanomaterials such as carbon nanotubes and two-dimensional semiconductors. They all have limitations originating in either intrinsic material properties or extrinsic defects introduced during processing, creating a mismatch between the bottom layer of silicon transistors built on the starting silicon wafer substrate and those upper layers.
The Illinois Grainger Engineering team devised a process that achieves monolithic three-dimensional integration using standard single-crystal silicon. The method starts with creating ultrathin, freestanding silicon nanomembranes from a doner wafer, and these membranes are then transferred onto the receiving substrate that already contains completed bottom-layer circuits using a roll laminator. The process requires no more than 200 degrees Celsius to generate a strong bond between the substrate and the transferred layer. As a result, high performance and reliability were maintained with the high crystalline quality of the silicon films while the process stayed well within the thermal budget.
“Our method is not only easier to implement with lower cost, but it has several advantages over previous approaches to stack silicon wafers,” Cao said. “The membranes we transferred are only 10 nanometers thick or less, compared to the 500 to 700 micrometers thickness of a typical wafer. Because they are thin, these membranes are mechanically flexible to conform to the underlying surface. This conformality helps avoid interfacial defects like voids, which are common when trying to force two rigid wafers together via wafer bonding.”
The team also needed to rethink transistor design and fabrication. Conventional transistor fabrication requires a process known as “doping” to introduce impurities to the silicon to control its electrical properties. This is a high-temperature process typically exceeding 600 degrees Celsius, and different regions of the device need to be doped differently. To avoid this, the researchers used devices called “junctionless transistors” in which the silicon is uniformly and heavily doped before the layering step. Because the films are extremely thin, the gate can still control the channel effectively, while the high doping level reduces parasitic contact resistance.
Using this process, the team built three stacked layers, each containing 625 transistors, with good yield and uniformity. The output current densities of these transistors were comparable to that of standard silicon transistors fabricated on bulk wafers under a much higher temperature and at least three to four times greater than those of monolithic devices made from alternative materials, indicating a substantial improvement in performance. By connecting the layers with vertical metal lines, the researchers demonstrated three-dimensional integrated logic circuits and static random-access memory cells.
“But most importantly, we’ve shown that this process is scalable,” Cao said. “You can keep stacking layers beyond the three we demonstrated. And the process will yield high-performing transistors with high yield and low variability. We now have a strong foundation for transferring this technology and demonstrating its immediate promise in an industrial semiconductor foundry.”
Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian-Min Zhuo also contributed to this study.
The article, “Monolithic three-dimensional integration of silicon transistors,” is available online. DOI: 10.1038/s41586-026-10496-6
Support was provided by the National Science Foundation, industry partners of the Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, and the Silicon Crossroads Microelectronics Commons Hub.
Illinois Grainger Engineering Affiliations
Qing Cao is an Illinois Grainger Engineering associate professor of materials science and engineering in the Department of Materials Science and Engineering. He is also affiliated with the Department of Electrical and Computer Engineeringand the Department of Chemistry. He is a member of the Materials Research Laboratory and the Holonyak Micro and Nanotechnology Laboratory.
Shaloo Rakheja is an Illinois Grainger Engineering associate professor of electrical and computer engineering in the Department of Electrical and Computer Engineering. She is the director of the Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). She is a member of the Holonyak Micro and Nanotechnology Lab and Coordinated Science Laboratory. She holds the Intel Alumni Endowed Faculty Fellow appointment.
Jian-Min Zhuo is an Illinois Grainger Engineering Professor Emeritus of materials science and engineering in the Department of Materials Science and Engineering.